EE|Times: International Solid-State Circuits Conference – Samsung big.little, but no Intel, Nvidia CPUs

Samsung will describe the first mobile applications processor to use ARM’s big.little concept at the International Solid-State Circuits Conference in February.

That’s one of only a few major new microprocessor disclosures at the semiconductor industry’s premier conference where Intel’s Haswell and Nvidia’s Project Denver parts are noticeably absent. However, both Intel and Nvidia will deliver papers on new chip-to-chip links that may provide an oblique view on their future processor plans.

Samsung will detail a 28-nm SoC with two quad-core clusters. One cluster runs at 1. 8 GHz, has a 2 MByte L2 cache and is geared for high performance apps; the other runs at 1.2 GHz and is tuned for energy efficiency.

The chip clearly parallel’s ARM’s description of a big.little architecture using its 32-bit A15 and A7 cores. In October, ARM said the approach is delivering greater than expected benefits and expects it will become widely used in smartphones.

“We expect the Samsung part is the first big.little processor,” said Kevin Krewell, senior analyst with market watcher Linley Group (Mountain View, Calif.). “The A7 cores should be capable of handling most [smartphone] tasks, with the A15 cores only required for maximum performance needs, like video games,” he said.

The chip and ones like it from Qualcomm, Nvidia and others will roll out in 2013, competing for sockets in tablets with Intel’s 22-nm Haswell, which will not be described at ISSCC. In a departure from past years, Intel will present no processor papers at the event.

However, the x86 giant will describe a scalable 64-lane chip-to-chip interconnect with 1 Tbit/s aggregate bandwidth. The link uses multiple 2-16 Gbit/s channels running at power efficiencies of 0.8 to 2.6 pJ/bit in 32nm CMOS with a total bus-level power consumption of 2.6 W.

The paper describes research at Intel Labs that is not necessarily related to a clustering interconnect the company announced in September for future x86 and Atom server processors. It describes research using so-called micro-twinax wiring from Samtec, and connectors from Ardent Concepts to link chips at Tbit/s rates that otherwise might draw up to 20 W, according to co-author Bryan Casper, a senior principal engineer overseeing I/O research at Intel Labs.

The 1 to 2 millimeter diameter wire bundles will be “a very important technology for us going forward for some segments” spanning mobile and server apps, said Casper. “Sub picojoule per bit I/O is really important, as are fast on and off I/O links.”

Separately, NVidia will describe a 20 Gbit/s serial die-to-die link made in 28-nm CMOS. It runs on a 0.9 V supply and has power efficiency of 0.54pJ/b. The interconnect might be part of Nvidia’s Project Denver, a still secretive family of processors merging ARM and graphics cores for everything from notebooks to supercomputers.

“It could be part of Project Denver or a technology to connect multiple GPUs together for Tesla-based supercomputer support,” said Krewell of Linley Group. “I haven’t heard any details of how Project Denver is proceeding, but Nvidia certainly needs to develop high performance interfaces that can connect arrays of Project Denver heterogeneous processors.”

Nvidia’s graphics chips are already widely used in massive clusters for supercomputers, including the world’s current fastest system called Titan.

Separately, China’s Institute of Computing Technology will describe a new version of the Godson 3B processor made using a 32-nm process. Previously ICT showed eight-core 65-nm CPUs and suggested it would leapfrog to 28-nm designs.

At ISSCC, engineers will detail Godson-3B1500, a 32-nm high-K, metal gate part delivering 172.8 Gflops when running at 1.35 GHz at 40 W. That’s up from 128 Gflops for the 65-nm version also drawing 40 W, thanks to the new process as well as architecture and circuit enhancements.

Among other papers, Texas Instruments and MIT will describe a 200-MHz video decoder implementing the High-Efficiency Video Coding draft standard to deliver 249 Mpixels/s. It enables 3840 x 2160 pixel resolution while consuming 76 mW at 0.9 V.

Renesas will describe a 28-nm integrated handset SoC with a dual-core 1.5 GHz CPU, an LTE/HSPA+ baseband modem processor, graphics accelerators and a power management unit. AMD, IBM and Oracle will present papers on their Jaguar, zSeries and Sparc T5 processors already described in August at Hot Chips.


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